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(R)
74VHC273
OCTAL D-TYPE FLIP FLOP WITH CLEAR
PRELIMINARY DATA
s
s
s
s s
s
s
s
s s
HIGH SPEED: fMAX = 165 MHz (TYP.) at VCC = 5V LOW POWER DISSIPATION: ICC = 4 A (MAX.) at TA = 25 oC HIGH NOISE IMMUNITY: VNIH = VNIL = 28% VCC (MIN.) POWER DOWN PROTECTION ON INPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 8 mA (MIN) BALANCED PROPAGATION DELAYS: tPLH tPHL OPERATING VOLTAGE RANGE: VCC (OPR) = 2V to 5.5V PIN AND FUNCTION COMPATIBLE WITH 74 SERIES 273 IMPROVED LATCH-UP IMMUNITY LOW NOISE VOLP = 0.9V (Max.)
M (Micro Package)
T (TSSOP Package)
ORDER CODES : 74VHC273M 74VHC273T Information signals applied to D inputs are transfered to the Q outputs on the positive going edge of the clock pulse. When the CLEAR input is held low, the Q outputs are held low independently of the other inputs . Power down protection is provided on all inputs and 0 to 7V can be accepted on inputs with no regard to the supply voltage. This device can be used to interface 5V to 3V. All inputs and outputs are equipped with protection circuits against static discharge, giving them 2KV ESD immunity and transient excess voltage.
DESCRIPTION The 74VHC273 is an advanced high-speed CMOS OCTAL D-TYPE FLIP FLOP WITH CLEAR fabricated with sub-micron silicon gate and double-layer metal wiring C2MOS technology.
PIN CONNECTION AND IEC LOGIC SYMBOLS
October 1999
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INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION
PIN No 1 2, 5, 6, 9, 12, 15, 16, 19 3, 4, 7, 8, 13, 14, 17, 18 11 SYMBOL CLEAR Q0 to Q7 NAME AND FUNCT ION Asyncronous Master Reset (Active LOW) Flip-Flop Outputs
D0 to D7
Data Inputs
CLOCK
Clock Input (LOW-to-HIGH, EdgeTriggered) Ground (0V) Positive Supply Voltage
10 20
GND VCC
TRUTH TABLE
INPUTS CL EAR L H H H
X:Don't Care
OUT PUT S CLO CK X Q L L H Qn
F UNCTIO N CLEAR
D X L H X
NO CHANGE
LOGIC DIAGRAMS
Thislogic diagram has notbe used to esimate propagation delays
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ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Current Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7.0 -0.5 to +7.0 -0.5 to VCC + 0.5 - 20 20 25 75 -65 to +150 300 Unit V V V mA mA mA mA
o o
ICC or IGND DC VCC or Ground Current
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition is not implied.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top dt/dv Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (see note 1) (VCC = 3.3 0.3V) (V CC = 5.0 0.5V) Parameter Valu e 2.0 to 5.5 0 to 5.5 0 to VCC -40 to +85 0 to 100 0 to 20 Unit V V V
o
C
ns/V ns/V
1) VIN from 30% to70%of VCC
DC SPECIFICATIONS
Symb ol Parameter T est Cond ition s V CC (V) VIH VIL VOH High Level Input Voltage Low Level Input Voltage High Level Output Voltage 2.0 3.0 to 5.5 2.0 3.0 to 5.5 2.0 3.0 4.5 3.0 4.5 VOL Low Level Output Voltage 2.0 3.0 4.5 3.0 4.5 II ICC Input Leakage Current Quiescent Supply Current 0 to 5.5 5.5 IO=-50 A IO=-50 A IO=-50 A IO=-4 mA IO=-8 mA IO=50 A IO=50 A IO=50 A IO=4 mA IO=8 mA VI = 5.5V or GND VI = VCC or GND 1.9 2.9 4.4 2.58 3.94 0.0 0.0 0.0 0.1 0.1 0.1 0.36 0.36 0.1 4 2.0 3.0 4.5
o
Value T A = 25 C Min. 1.5 0.7VCC 0.5 0.3VCC 1.9 2.9 4.4 2.48 3.8 0.1 0.1 0.1 0.44 0.44 1.0 40 Typ . Max. -40 to 85 C Min . 1.5 0.7VCC 0.5 0.3VCC Max.
o
Un it
V V
V
V
A A
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AC ELECTRICAL CHARACTERISTICS (Input t r = tf =3 ns)
Symb ol Parameter V CC (V) tPLH tPHL Propagation Delay Time CK to Q Test Co ndition CL (pF ) 15 50 15 50 15 50 15 50 Value T A = 25 o C Min. Typ . Max. 8.7 13.6 11.2 5.8 7.3 8.9 11.4 5.2 6.7 17.1 9.0 11.0 13.6 17.1 8.5 10.5 5.0 5.0 5.5 5.0 5.5 4.5 1.0 1.0 2.5 2.0 15 50 15 50 50 50 75 50 120 80 120 75 165 110 1.5 1.0 65 45 100 70 1.5 1.0 ns MHz Un it -40 to 85 o C Min . Max. 1.0 16.0 1.0 1.0 1.0 1.0 1.0 1.0 1.0 19.5 10.5 12.5 16.0 19.5 10.0 12.0 6.0 5.0 6.5 5.0 6.5 4.5 1.0 1.0 2.5 2.0 ns ns ns ns ns ns
3.3(*) 3.3(*) 5.0(**) 5.0(**) 3.3(*) 3.3(*) 5.0 5.0(**) 3.3 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 5.0(**) 3.3(*) 3.3 5.0(**) 5.0 3.3(*)
(**) (*) (*) (**)
tPHL
Propagation Delay Time CLR to Q
ns
tw tw ts th tREM fMAX
CLR pulse Width LOW CK pulse Width HIGH or LOW Setup Time D to CK HIGH or LOW Hold Time D to CK HIGH or LOW Removal Time CLR to CK Maximum Clock Frequency
tOSLH tOSHL
Output to Output Skew Time (note 1)
5.0(**)
(*) Voltage range is 3.3V 0.3V (**) Voltage range is 5V 0.5V Note 1: Parameter guaranteed by design. tsoLH = |tpLHm- tpLHn|, tsoHL = |tpHLm - tpHLn|
CAPACITIVE CHARACTERISTICS
Symb ol Parameter T est Cond ition s
o
Value T A = 25 C Min. Typ . Max. -40 to 85 C Min . Max. 10
o
Un it
C IN CPD
Input Capacitance Power Dissipation Capacitance (note 1)
4 31
10
pF pF
1) CPD isdefined as the value of the IC'sinternal equivalent capacitance which is calculated fromthe operating current consumption without load. (Referto Test Circuit).Average operating current can be obtained by the following equation. ICC(opr) = CPD * VCC * fIN + ICC/8 (per Flip-Flop)
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DYNAMIC SWITCHING CHARACTERISTICS
Symb ol Parameter T est Cond ition s V CC (V) VOLP VOLV VIHD VILD Dynamic Low Voltage Quiet Output (note 1, 2) Dynamic High Voltage Input (note 1, 3) Dynamic Low Voltage Input (note 1, 3) 5.0 -0.9 5.0 5.0 C L = 50 pF 3.5 1.5 Min. Typ . 0.6 -0.6 V Value T A = 25 o C Max. 0.9 -40 to 85 o C Min . Max. Un it
1) Worst case package. 2) Max number of outputs defined as (n). Data inputs are driven 0V to 5.0V, (n -1) outputs switching and one output at GND. 3) Max number of data inputs (n) switching. (n-1) switching 0V to5.0V. Inputs under test switching: 5.0V to threshold (VILD), 0V to threshold (VIHD), f=1MHz.
TEST CIRCUIT
CL = 15/50 pF or equivalent (includes jig and probe capacitance) RT = ZOUT of pulse generator (typically 50)
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WAVEFORM 1: PROPAGATION DELAYS, SETUP AND HOLD TIMES (f=1MHz; 50% duty cycle)
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WAVEFORM 2: PROPAGATION DELAYS (f=1MHz; 50% duty cycle)
WAVEFORM 3: RECOVERY TIME (f=1MHz; 50% duty cycle)
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SO-20 MECHANICAL DATA
DIM. MIN. A a1 a2 b b1 C c1 D E e e3 F L M S 7.40 0.50 12.60 10.00 1.27 11.43 7.60 1.27 0.75 8 (max.) 0.291 0.19 13.00 10.65 0.35 0.23 0.50 45 (typ.) 0.496 0.393 0.050 0.450 0.299 0.050 0.029 0.512 0.419 0.10 mm TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012
P013L
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TSSOP20 MECHANICAL DATA
mm MIN. A A1 A2 b c D E E1 e K L 0o 0.50 0.05 0.85 0.19 0.09 6.4 6.25 4.3 6.5 6.4 4.4 0.65 BSC 4o 0.60 8o 0.70 0o 0.020 0.10 0.9 TYP. MAX. 1.1 0.15 0.95 0.30 0.2 6.6 6.5 4.48 0.002 0.335 0.0075 0.0035 0.252 0.246 0.169 0.256 0.252 0.173 0.0256 BSC 4o 0.024 8o 0.028 0.004 0.354 MIN. inch TYP. MAX. 0.433 0.006 0.374 0.0118 0.0079 0.260 0.256 0.176
DIM.
A
A2 A1 b e K c L E
D
E1
PIN 1 IDENTIFICATION
1
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Information furnished is believed to be accurate and reliable. However, STMicroelectronic s assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems withoutexpress written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 1999 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com .
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